Three bits of data will load into Q A Q B D C at the same time. The upper NAND gates serving D A D B D C are enabled, passing data to the D inputs of type D Flip-Flops Q A Q B D C respectively.Īt the next positive going clock edge, the data will be clocked from D to Q of the three FFs. We show three stages due to space limitations.įour, eight or sixteen bits is normal for real parts.Ībove we show the parallel load path when SHIFT/LD’ is logic low. In general, these elements will be replicated for the number of stages required. By parallel format we mean that the data bits are present simultaneously on individual wires, one for each data bit as shown below.īy serial format we mean that the data bits are presented sequentially in time on a single wire or circuit as in the case of the “data out” on the block diagram below.īelow we take a close look at the internal details of a 3-stage parallel-in/ serial-out shift register.Ī stage consists of a type D Flip-Flop for storage, and an AND-OR selector to determine whether data will load in parallel, or shift stored data to the right. This is a way to convert data from a parallel format to a serial format. In addition, parallel-in/ serial-out really means that we can load data in parallel into all stages before any shifting ever begins. The parallel-in/ serial-out shift register stores data, shifts it on a clock by clock basis, and delays it by the number of stages times the clock period.
library ieee use ieee.std_logic_1164.Parallel-in/ serial-out shift registers do everything that the previous serial-in/ serial-out shift registers do plus input data to all stages simultaneously. library ieee use ieee.std_logic_1164.all entity shift is port(C, SI : in std_logic SO : out std_logic) end shift architecture archi of shift is signal tmp: std_logic_vector(7 downto 0) begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) = tmp(i) end loop tmp(0) = SI end if end process SO = tmp(7) end archi Following is the VHDL code for an 8-bit shift-left register with a negative-edge clock, clock enable, serial in, and serial out.
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.
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